Fix my previous patch to the trap-frame creation code
authorkaf24@firebug.cl.cam.ac.uk <kaf24@firebug.cl.cam.ac.uk>
Thu, 4 Aug 2005 17:37:09 +0000 (17:37 +0000)
committerkaf24@firebug.cl.cam.ac.uk <kaf24@firebug.cl.cam.ac.uk>
Thu, 4 Aug 2005 17:37:09 +0000 (17:37 +0000)
in Xen. I was clobbering an in-use register (AL): use
CH instead.
Signed-off-by: Keir Fraser <keir@xensource.com>
xen/arch/x86/x86_32/entry.S
xen/arch/x86/x86_64/entry.S

index 52a5449f74929f248bc50bbaedbeba6148f940d1..99d5b1fbc28bb2397f6102afd3030a797d2e6a28 100644 (file)
@@ -335,8 +335,8 @@ FLT14:  movl %eax,%gs:(%esi)
         movl VCPU_vcpu_info(%ebx),%eax
         pushl VCPUINFO_upcall_mask(%eax)
         testb $TBF_INTERRUPT,%cl
-        setnz %al                        # TBF_INTERRUPT -> set upcall mask
-        orb  %al,VCPUINFO_upcall_mask(%eax)
+        setnz %ch                        # TBF_INTERRUPT -> set upcall mask
+        orb  %ch,VCPUINFO_upcall_mask(%eax)
         popl %eax
         shll $16,%eax                    # Bits 16-23: saved_upcall_mask
         movw UREGS_cs+4(%esp),%ax        # Bits  0-15: CS
index d71e38ace481bdc32cd48ab315e9ee078fd25203..a8a5574e2c86d12ef4d620ee0f8a629ff33b71c8 100644 (file)
@@ -314,8 +314,8 @@ FLT4:   movq  %rax,16(%rsi)             # RFLAGS
         movq  VCPU_vcpu_info(%rbx),%rax
         pushq VCPUINFO_upcall_mask(%rax)
         testb $TBF_INTERRUPT,%cl
-        setnz %al                       # TBF_INTERRUPT -> set upcall mask
-        orb   %al,VCPUINFO_upcall_mask(%rax)
+        setnz %ch                       # TBF_INTERRUPT -> set upcall mask
+        orb   %ch,VCPUINFO_upcall_mask(%rax)
         popq  %rax
         shlq  $32,%rax                  # Bits 32-39: saved_upcall_mask
         movw  UREGS_cs+8(%rsp),%ax      # Bits  0-15: CS